1. Field of the Invention
This invention relates to direct digital synthesis (DDS) and more specifically to a dual-tunable direct digital synthesizer with a frequency programmable clock and a method of tuning to reduce power consumption and/or spur noise.
2. Description of the Related Art
DDS is a technique for synthesizing, under digital control, a periodic analog waveform from a fixed reference clock signal. The waveform frequency F.sub.o is given by: EQU F.sub.o =(F.sub.n /2.sup.N).times.F.sub.clk ( 1)
where N is the resolution of the digital control word, the tuning word F.sub.n is the value of the N-bit control word and represents the phase increment, and F.sub.clk is the frequency of the reference clock signal. The reference clock frequency F.sub.clk must be at least twice the maximum waveform frequency F.sub.o to satisfy the Nyquist criterion, and, as a rule of thumb, is three to four times the maximum waveform frequency to shift the harmonically related spurs or aliased images away from the fundamental. Once the clock frequency is fixed, the tuning word F.sub.n uniquely determines the waveform frequency.
Garvey et al. "An Exact Spectral Analysis of a Number Controlled Oscillator Based Synthesizer," Fourty-Fourth Annual Symposium on Frequency Control, pp. 511-521, 1990 and V. Manassevitsch, Frequency Synthesizers Theory and Design, Wiley Interscience 3.sup.rd Edition, pp. 37-43, 1987 describe the well known DDS architecture. A stable crystal-controlled oscillator generates the fixed frequency reference clock signal F.sub.clk while a frequency tuner outputs the tuning word F.sub.n, which sets the step-size of a programmable phase accumulator. At each clock cycle, the accumulator output represents the instantaneous phase of the periodic analog waveform. The phase is then converted to a periodic digital waveform either by direct computation or by using a look-up table (LUT) . A DAC converts the digital waveform into the desired analog waveform, which is passed through a low pass filter to remove the aliased components induced by the sampling process and the higher order harmonics.
In effect, a DDS system divides the reference clock signal down in frequency by some number K=2.sup.N /F.sub.n greater than 2 and converts it to a desired waveform. Dividing down the frequency in this manner provides extremely fine frequency resolution, fast frequency switching, and reduces the phase noise in the waveform by 20 log.sub.10 K. Although generally superior to other synthesis techniques in frequency resolution and update capabilities, DDS high frequency operation, power consumption and spurious noise performance bear improvement.
Specifically, high frequency operation is currently impractical due to the cost of providing a very high frequency reference clock signal, the noise coupling associated with running the high frequency clock signal across the circuit board, and the power consumption. The reference clock signal consumes power at the level required to generate the maximum waveform frequency, regardless of the actual waveform frequency. Finally, the quantization level errors inherent in a DDS process produce a different spurious noise pattern for each tuning word value, which can be further degraded by any nonlinearities in the DAC. The spur patterns exhibit narrow frequency bands or "enhanced dynamic range bands" at which the synthesizer's Spurious Free Dynamic Range (SFDR) meets the noise specifications for the output waveform. As a result, known DDS systems are constrained to generate output frequencies that lie only inside these enhanced dynamic range bands or tolerate a reduced SFDR. This seriously comprises the flexibility and performance of known systems.